In semiconductor design, particularly SRAM design, it is often desirable to create a contact bridge between contacts in very close proximity. In particular, contact areas (CAs) are connected together to form complex circuits from basic transistors. For example, the gate of one transistor may be connected to the drain or source of another transistor.
Modern semiconductor devices typically have multiple levels of metal interconnects. The metal interconnects are typically formed via a deposition and patterning sequence as is known in the art. During the process of forming interconnects, defects, such as CA opens and CA shorts decrease the overall production yield. Various parameters affect the probabilities of CA opens and CA shorts. Moving a process window in one direction may reduce the number of CA opens, but increase the number of CA shorts. There is an inherent tradeoff in semiconductor manufacturing between the number of CA shorts and the number of CA opens.
In current semiconductor fabrication techniques, a process window is optimized for only one parameter at a time, and the tradeoff between CA opens and CA shorts is not well accounted for. For example, if a CD (critical dimension) process window is optimized, this will require a shift in the oxide thickness process window. However, if the oxide thickness process window is to be optimized, the CD process window will then shift. This can adversely affect the overall production yield. Therefore, what is desired is a technique for improved process window optimization, which will in turn improve overall production yields in semiconductor manufacturing.